Metric Noise Resource (MNR)

Motivation

The Metric-Noise-Resource (MNR) methodology was introduced in 2022 by M. Fellous-Asiani et al. [1] in the context of the Quantum Energy Initiative [2]. The authors motivate the creation of this methodology by the need for a multi-level approach to understand and optimize the resource consumption of quantum computers. As explained by the authors, such an approach requires a strong knowledge of quantum processors at a physical level (e.g., quantum control) and at a software level (e.g., quantum error correction and quantum algorithms). This methodology aims to obtain a clear view of how resources will scale with the size of the computational task.

Methodology

The MNR methodology aims to minimize the resources \(\mathcal{R}\) required by a quantum computer to reach a specific target metric \(\mathcal{M}\) and to identify/analyse non-trivial tradeoffs between the parameters under study. This minimization is done with respect to the determined control parameters.

Methodology’s components

The MNR methodology comprises several components (see the figure for the dependency between the main components):

Component dependancy in the Metric Noise Resource (MNR) methodology.

Applying MNR

The principle of the approach boils down to a minimization under constraints. One asks to minimize the resource spent by the computation, under the constraints that the performance metric is larger or equal to a target value \(M_0\). This target guarantees the computation is sufficiently accurate. The minimization is performed by varying the control parameters.
Solving the minimization allows finding optimal values for the control parameters so that the architecture minimizes the spent resources while guaranteeing the computation is sufficiently successful.
The main interest of the approach is that it allows for holistically optimizing the computer as the controllable parameter can come from software aspects (amount of error-correction), or hardware ones (speed of the gates, temperature of the qubits, etc). As explained in various examples below, it allows for resolving non-trivial tradeoffs when the architecture is optimized.

Implementation Examples

Different examples using this methodology are given in the initial paper [1]. These examples use simplified models to provide insights about resource consumption scaling. Below, we follow the logic of the paper, which introduces three simple pedagogic examples, optimizing the consumption of single-qubit gates, before going to the detailed example of the optimization of a full-stack model of a fault-tolerant quantum computer, implementing Shor’s algorithm with superconducting qubits.

Noisy single-qubit gate implementation (quantum-level)

Section III. A of [1] minimizes the power consumption of quantum gates to reach a satisfying fidelity. It studies the tradeoffs between:

A sweet spot to the gate duration is found during the optimization: it shouldn’t be too long because it would be too noisy, but not too short because it would then lead to a too high consumption. Applying the MNR methodology resolves this tradeoff and finds the minimum power (and optimized control parameters) to implement the gate with the targeted fidelity.

The following parameters are considered:

Noisy single-qubit gate implementation (macroscopic-level)

Section III. B of [1] minimizes the power consumption, including higher-level controls and the cryostat. The control parameters are the temperature of the qubits in the cryostat and the attenuation factor. Modifying these two control parameters allows for mitigating thermal noise but at an increasing cost in power consumption, leading to a tradeoff that needs to be resolved.

The following parameters are considered:

As one can see, there is a tension between asking for low noise and low consumption by tuning the control parameters. Applying the MNR methodology allows finding the optimal qubit’s temperature and attenuation so that the consumption is minimized under the constraint that the gate fidelity is at least equal to some target.

Circuit compression degree

Section IV of [1] studies the degree of compression of the quantum circuit and its impact on the power consumption of the quantum computer. It highlights the tradeoffs between:

As the circuit gets compressed, its fidelity increases because qubits have only short idling times. However, the more compressed it becomes, the more parallel gates are implemented, increasing the system’s power consumption. It leads to the aforementioned tradeoff. The following parameters are considered:

In this example, the optimal qubit’s temperature, attenuation, and circuit compression are found so that the consumption is minimized under the constraint that the circuit fidelity is at least equal to some acceptable target.

Fault-tolerant factorization

Section V of [1] studies the potential advantage of a quantum computer implementing Shor’s algorithm using the Steane code (a fault-tolerant quantum error correction code) for superconducting qubits. The authors emphasize that the model is highly idealized (very optimistic qubit qualities). For this reason, this example should be understood as a proof of concept of how to apply the methodology in a complete model of fault-tolerant quantum computing, rather than a precise estimate based on near-term qubits.
The following parameters are considered:

In this example, the optimal qubit’s temperature, attenuation, number of physical per logical qubits (more formally, the concatenation level), and signal generation’s temperature are found so that the power consumption of the computer is minimized under the constraints that the algorithm is implemented with a sufficiently high targeted success probability.

Interestingly, the authors show that it is sometimes energetically more interesting to put qubits at a higher temperature and compensate for the extra noise induced by doing more error-correction than what a typical estimate would indicate. Their work also suggests that in a specific regime, the quantum computer could factor RSA using more time than a classical computer, but consuming less energy.

References

  1. [1]M. Fellous-Asiani, J. H. Chai, Y. Thonnart, H. K. Ng, R. S. Whitney, and A. Auffèves, “Optimizing Resource Efficiencies for Scalable Full-Stack Quantum Computers,” PRX Quantum, vol. 4, no. 4, Oct. 2023, doi: 10.1103/prxquantum.4.040319. [Online]. Available at: http://dx.doi.org/10.1103/PRXQuantum.4.040319
  2. [2]A. Auffèves, “Quantum Technologies Need a Quantum Energy Initiative,” PRX Quantum, vol. 3, no. 2, Jun. 2022, doi: 10.1103/prxquantum.3.020101. [Online]. Available at: http://dx.doi.org/10.1103/PRXQuantum.3.020101

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